Power-and-ground (PG) network characterization and distributed PG network creation for hierarchical circuit designs
US9747403B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2015 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Oct 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A chip layout can include a top-level portion and a set of blocks. The power-and-ground (PG) network for the chip layout can be specified by a set of chip-level PG constraints that is defined using a PG constraint definition language. The set of chip-level PG constraints can be characterized into new sets of PG constraints that correspond to smaller regions of the chip layout, e.g., a set of top-level PG constraints that corresponds to the top-level portion, and a set of block-level PG constraints for each block in the set of blocks. The new sets of PG constraints can then be provided to one or more instances of a PG compiler that executes on one or more processors to create the PG network for the chip layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.