Package and method of manufacturing the same
US9748179B2 · kind B2 · utility
4Cited by
16References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2015 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Jul 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The package includes: a substrate having at least one circuit layer; at least one electronic component mounted on at least one surface of the substrate; a molded part formed on the surface of the substrate to enclose the electronic component; at least one via formed in the molded part to be electrically connected to the circuit layer of the substrate; and a pattern connected to one end of a plated tail connected to the circuit layer connected to the via and exposed to the exterior of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.