Manufacture method of dual gate oxide semiconductor TFT substrate and structure thereof
US9748285B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2015 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Sep 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1213
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a manufacture method of an oxide semiconductor TFT substrate and a structure thereof. The manufacture method of the dual gate oxide semiconductor TFT substrate utilizes the halftone mask to implement one photo process, which cannot only accomplish the patterning to the oxide semiconductor layer but also obtain the oxide conductor layer (53′) with ion doping process; the method implements the patterning process to the bottom gate isolation layer (31) and the top gate isolation layer (32) at the same time with one photo process; the method implements patterning process to the second, third metal layers at the same time to obtain the first source (81), the first drain (82), the second source (83), the second drain (84), the first top gate (71) and the second top gate (72) with one photo process; the method implements patterning process to the second flat layer (9), the passivation layer (8) and the top gate isolation layer (32) at the same time with one photo process, to reduce the number of the photo processes to nine for effectively simplifying the manufacture process, raising the production efficiency and lowering the production cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.