Method and apparatus for source-synchronous signaling
US9748960B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2014 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Dec 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0087
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.