Apparatus and method to reduce power losses in an integrated voltage regulator
US9753510B2 · kind B2 · utility
2Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2015 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Sep 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/1586
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.