Patent · US Active

Systems, apparatuses, and methods for synchronizing port entry into a low power status

US9753529B2 · kind B2 · utility

2Cited by

0References

26Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Mahesh Wagh · Portland, US
Su Wei Lim · Klang, MY

Key dates

Filing date	May 18, 2016
Grant date	Sep 5, 2017
Priority date	—
Expiry date	May 18, 2036

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D30/70
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Systems, apparatuses, and method for synchronizing port entry into a lowest power state are described. All logic of a port placed into an intermediate state prior to entry into the lowest power state.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.