Input output value prediction with physical or virtual addressing for virtual environment
US9753859B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2015 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Jan 20, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/654
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and system embodying the method for input/output value determination at a processor core, comprising generating an I/O instruction comprising at least a physical or a virtual address; comparing the address with a relevant database of I/O devices addresses. When the comparing is successful determining the I/O device or a state on the I/O device to receive the I/O instruction in accordance with the address; setting a value of a first register to a value identifying the determined I/O device or the state on the I/O device; predicting a value to be set in a second register in accordance with the address; and setting a value of a third register. Providing I/O instruction other than a request I/O instruction to the I/O device or the state on the I/O device, which sets a register to a value according to the I/O instruction and reports the value to the processor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.