Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices
US9754065B2 · kind B2 · utility
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Key dates
| Filing date | Oct 11, 2013 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Sep 11, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.