Layout optimization for integrated circuit design
US9754073B2 · kind B2 · utility
0Cited by
8References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 15, 2016 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Aug 15, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.