Semiconductor transistor device and fabrication method thereof
US9754828B1 · kind B1 · utility
2Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2016 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Jul 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a gate, a spacer on a sidewall of the gate, a doping region on one side of the gate, an insulating cap layer covering the gate, the spacer and the doping region, and a redistributed contact layer (RCL) on the insulating cap layer. The RCL extends from the active area to the trench isolation region. A contact plug is disposed above the trench isolation region and is electrically connected to the gate or the doping region through the RCL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.