Patent · US Active

Semiconductor structure and fabrication method thereof

US9754893B2 · kind B2 · utility

5Cited by

3References

10Claims

0Family size

Assignee

Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

Jingxiu Ding · Shanghai, CN
Zuopeng He · Shanghai, CN

Key dates

Filing date	Sep 22, 2015
Grant date	Sep 5, 2017
Priority date	—
Expiry date	Sep 22, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/20109
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Semiconductor structure and fabrication methods are provided. The semiconductor structure includes a first wafer having a first metal layer therein and having a first material layer thereon, and a second wafer having a second metal layer therein and having a second material layer thereon. An alignment process and a bonding process are preformed between the first wafer and the second wafer, such that the first material layer and the second material layer are aligned and in contact with one another to provide a first alignment accuracy between the first metal layer and second metal layer. A heating process is performed on the first material layer and the second material layer to melt the first material layer and the second material layer to provide a second alignment accuracy between the first metal layer and second metal layer. The second alignment accuracy is greater than the first alignment accuracy.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.