Semiconductor memory device and method for manufacturing same
US9754961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2016 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Feb 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of insulating layers and including a first insulating layer and a plurality of conductive layers including a first conductive layer; a first semiconductor film extending in a stacking direction of the stacked body; a second semiconductor film, the second semiconductor film having a maximum thickness thicker than a maximum thickness of the first semiconductor film in a first direction crossing the stacking direction; and a first insulating film. The second semiconductor film has an upper face, and a height of the upper face is lower than a height of the first conductive layer. The first insulating film has a lower end portion, and a height of the lower end portion of the first insulating film is lower than the height of the upper face of the second semiconductor film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.