Vertical thin film transistors with surround gates
US9754999B1 · kind B1 · utility
1Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2016 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Aug 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A method is provided that includes forming a transistor by forming a gate disposed in a first direction above a substrate, the gate including a first bridge portion and a second bridge portion, forming the first bridge portion extending in the first direction and disposed near a top of the gate, and forming the second bridge portion extending in the first direction and disposed near a bottom of the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.