High throughput packet state processing
US9756154B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 13, 2014 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Dec 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for processing data includes a filtering module having a plurality of processing units, a state accumulator, and a merging network coupled to the processing units and the state accumulator. Each processing unit is configured to output a set of two sub-state vectors and a packet continuance indicator. The state accumulator is configured to store a state resulted from previous processing cycles by the processing units. The merging network is configured to output a master state vector based at least in part on the set of two sub-state vectors, the stored state, and the packet continuance indicators output from the processing units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.