Partially-bad block operation in 3-D nonvolatile memory
US9760303B2 · kind B2 · utility
2Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2015 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Feb 3, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Partially-bad blocks are identified in a 3-D block-erasable nonvolatile memory, each partially-bad block having one or more inoperable separately-selectable sets of NAND strings and one or more operable separately-selectable sets of NAND strings. Operable sets of NAND strings within two or more partially-bad blocks are identified and are mapped to form one or more virtual blocks that are individually assigned virtual block addresses. The virtual block address are maintained in a list and used to access the virtual blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.