Accelerating cache state transfer on a directory-based multicore architecture
US9760486B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 2016 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Mar 25, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies are generally described herein for accelerating a cache state transfer in a multicore processor. The multicore processor may include first, second, and third tiles. The multicore processor may initiate migration of a thread executing on the first core at the first tile from the first tile to the second tile. The multicore processor may determine block addresses of blocks to be transferred from a first cache at the first tile to a second cache at the second tile, and identify that a directory at the third tile corresponds to the block addresses. The multicore processor may update the directory to reflect that the second cache shares the blocks. The multicore processor may transfer the blocks from the first cache in the first tile to the second cache in the second tile effective to complete the migration of the thread from the first tile to the second tile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.