FeRAM-DRAM hybrid memory
US9761312B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 16, 2016 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Mar 16, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, where a first digit line coupled to the first memory cell is coupled to a paging buffer register including a sense amplifier. The method further includes operating a transfer gate based at least in part on determining to read the second memory cell of the second memory cell array, where the transfer gate is configured to selectively couple a second digit line coupled to the second memory cell to the paging buffer register through the first digit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.