Memory device layout, semiconductor device, and method of manufacturing memory device

US9761572B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Jui-Lin Chen · Taipei, TW
• Feng-Ming Chang · Kaohsiung, TW
• Huai-Ying Huang · Kaohsiung, TW
• Ping-Wei Wang · Baoshan, TW

Key dates

• Filing date: Apr 16, 2015
• Grant date: Sep 12, 2017
• Expiry date: Apr 16, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/12

Abstract

A layout of a memory device is stored on a non-transitory computer-readable medium. The layout includes a plurality of active area regions, a lowermost interconnect layer, a plurality of memory cells, and a word line. The lowermost interconnect layer includes a first conductive layer over the plurality of active area regions, and a second conductive layer over the first conductive layer. The plurality of memory cells includes the plurality of active area regions. The word line is in the second conductive layer, and is coupled to the plurality of memory cells.