Manufacturing of self aligned interconnection elements for 3D integrated circuits
US9761583B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2016 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Jun 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making connection elements between two different levels of components in a 3D integrated circuit, including: forming a lateral insulating area supported on at least one given conducting area among several interconnection areas on a first level of components, the insulating area extending around a semiconducting layer on a second level in which at least one transistor can be formed; removing a first portion of the lateral insulating area so as to form at least one hole exposing said given conducting area; and depositing a conducting material in the hole so as to form a first electrical connection element between the second component and the given conducting area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.