Semiconductor memory device
US9761602B2 · kind B2 · utility
9Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2015 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Aug 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
A semiconductor memory device to which a Peri Under Cell (PUC) structure is applied is disclosed. The semiconductor memory device includes a word line multilayered structure formed in a cell region, and extending from across the cell region; and a slimming region including a step-shaped pad structure in the word line multilayered structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.