Metal-oxide-semiconductor transistor and method of forming gate layout
US9761657B2 · kind B2 · utility
6Cited by
2References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 25, 2015 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Nov 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A metal-oxide-semiconductor transistor includes a substrate, a gate insulating layer disposed on the surface of the substrate layer, a metal gate disposed on the gate insulating layer and having at least one plug hole, at least one dielectric plug disposed in the plug hole, and two diffusion regions disposed at two sides of the metal gate in the substrate. The metal gate is configured to operate under an operation voltage greater than 5 v.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.