Vertical transistors with merged active area regions
US9761712B1 · kind B1 · utility
14Cited by
5References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2016 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Oct 31, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for device layout with vertical transistors includes identifying active area regions in a layout of a semiconductor device with vertical transistors. Sets of adjacent active area regions having a same electrical potential are determined. The sets of adjacent active area regions to be merged are prioritized based upon one or more performance criterion. The sets of adjacent active area regions are merged to form larger active area regions according to a priority.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.