Isolation of bulk FET devices with embedded stressors

US9761722B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Hemanth Jagannathan · Niskayuna, US
• Nicolas Loubet · Guilderland, US

Key dates

• Filing date: Jun 24, 2016
• Grant date: Sep 12, 2017
• Expiry date: Jun 24, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

A field-effect transistor device and a method of isolating a field-effect transistor device. The method includes forming a layer of silicon germanium (SiGe) over a substrate, and fabricating a dummy gate stack above a silicon layer formed on the layer of SiGe. Etching the silicon layer defines a channel region below the dummy gate stack. The channel is isolated from the substrate by forming a cavity between the channel region and the substrate below the channel region, the cavity extending over a length of the channel region, wherein the length of the channel region extends from a source region to a drain region below the dummy gate stack. The cavity is filled with an oxide and a low K spacer material to isolate the channel region from the substrate.