Inventor · Guilderland, NY, US

Nicolas Loubet

283Patents
15h-index
143Co-inventors
85Inventor score

Filing activity: Feb 9, 2007 → Feb 28, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US9716158B1 Air gap spacer between contact and gate region Electricity 67 Active
US8569152B1 Cut-very-last dual-epi flow Electricity 59 Active
US9741626B1 Vertical transistor with uniform bottom spacer formed by selective oxidation Electricity 42 Active
US10074575B1 Integrating and isolating nFET and pFET nanosheet transistors on a substrate Electricity 35 Active
US8956942B2 Method of forming a fully substrate-isolated FinFET transistor Electricity 35 Active
US9755017B1 Co-integration of silicon and silicon-germanium channels for nanosheet devices Electricity 35 Active
US8759874B1 FinFET device with isolated channel Electricity 30 Active
US10388732B1 Nanosheet field-effect transistors including a two-dimensional semiconducting material Electricity 28 Active
US9761722B1 Isolation of bulk FET devices with embedded stressors Electricity 23 Active
US8975168B2 Method for the formation of fin structures for FinFET devices Electricity 19 Active
US10573755B1 Nanosheet FET with box isolation on substrate Electricity 18 Active
US9093496B2 Process for faciltiating fin isolation schemes Electricity 17 Active
US10109533B1 Nanosheet devices with CMOS epitaxy and method of forming Electricity 17 Active
US8952420B1 Method to induce strain in 3-D microfabricated structures Electricity 17 Active
US8592290B1 Cut-very-last dual-EPI flow Electricity 15 Active
US10276442B1 Wrap-around contacts formed with multiple silicide layers Electricity 13 Active
US7906381B2 Method for integrating silicon-on-nothing devices with standard CMOS devices Electricity 13 Active
US10424651B2 Forming nanosheet transistor using sacrificial spacer and inner spacers Electricity 12 Active
US10170520B1 Negative-capacitance steep-switch field effect transistor with integrated bi-stable resistive system Electricity 12 Active
US8900973B2 Method to enable compressively strained pFET channel in a FinFET structure by implant and thermal diffusion Electricity 12 Active
US8828851B2 Method to enable the formation of silicon germanium channel of FDSOI devices for PFET threshold voltage engineering Electricity 12 Active
US9166023B2 Bulk finFET semiconductor-on-nothing integration Electricity 11 Active
US10020398B1 Stress induction in 3D device channel using elastic relaxation of high stress material Electricity 10 Active
US9219078B2 Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs Electricity 10 Active
US9012999B2 Semiconductor device with an inclined source/drain and associated methods Electricity 10 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.