Apparatuses with an embedded combination logic circuit for high speed operations
US9762247B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 16, 2016 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Jun 16, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.