Selective segment via plating process and structure
US9763327B2 · kind B2 · utility
3Cited by
18References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2015 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Aug 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10303
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the inner core layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.