Controlling power consumption of a processor using interrupt-mediated on-off keying
US9766685B2 · kind B2 · utility
1Cited by
4References
19Claims
0Family size
Assignee
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Key dates
| Filing date | May 15, 2013 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Mar 7, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the on and off times vary depending on whether and when an interrupt is incurred. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.