Hardware synchronization barrier between processing units
US9766951B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2015 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | May 26, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/54
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for synchronizing multiple processing units, comprises the steps of configuring a synchronization register in a target processing unit so that its content is overwritten only by bits that are set in words written in the synchronization register; assigning a distinct bit position of the synchronization register to each processing unit; and executing a program thread in each processing unit. When the program thread of a current processing unit reaches a synchronization point, the method comprises writing in the synchronization register of the target processing unit a word in which the bit position assigned to the current processing unit is set, and suspending the program thread. When all the bits assigned to the processing units are set in the synchronization register, the suspended program threads are resumed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.