Patent · US Active

Secure memory repartitioning

US9767044B2 · kind B2 · utility

13Cited by

7References

25Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Siddhartha Chhabra · Portland, US
Uday Savagaonkar · Redmond, US
Michael A. Goldsmith · Lake Oswego, US
Simon P. Johnson · Beaverton, US
Rebekah M. Leslie-Hurd · Portland, US
Francis X. McKeen · Portland, US
Gilbert Neiger · Hillsboro, US
Raghunandan Makaram · Northborough, US
Carlos V. Rozas · Portland, US
Amy L. Santoni · Scottsdale, US
Vincent R. Scarlata · Beaverton, US
Vedvyas Shanbhogue · Austin, US
Wesley H. Smith · Raleigh, US
Ittai Anati · Ramat HaSharon, IL
Ilya Alexandrovich · Haifa, IL

Key dates

Filing date	Sep 24, 2013
Grant date	Sep 19, 2017
Priority date	—
Expiry date	Mar 21, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/152
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Secure memory repartitioning technologies are described. A processor includes a processor core and a memory controller coupled between the processor core and main memory. The main memory includes a memory range including a section of convertible pages that are convertible to secure pages or non-secure pages. The processor core, in response to a page conversion instruction, is to determine from the instruction a convertible page in the memory range to be converted and convert the convertible page to be at least one of a secure page or a non-secure page. The memory range may also include a hardware reserved section that is convertible in response to a section conversion instruction.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.