Semiconductor devices and methods of fabricating the same
US9768018B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2016 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Apr 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The inventive concepts provide semiconductor devices and methods of fabricating the same. According to the method, sub-stack structures having a predetermined height and active holes are repeatedly stacked. Thus, cell dispersion may be improved, and various errors such as a not-open error caused in an etching process may be prevented. A grain size of an active pillar used as channels may be increased or maximized using a metal induced lateral crystallization method, so that a cell current may be improved. A formation position of a metal silicide layer including a crystallization inducing metal may be controlled such that a concentration grade of the crystallization inducing metal may be controlled depending on a position within the active pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.