Method of forming a semiconductor structure
US9768029B2 · kind B2 · utility
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22References
11Claims
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Assignee
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Key dates
| Filing date | May 31, 2016 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Jun 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided. The dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench. A work function metal layer and a top barrier layer are sequentially formed in the gate trench. A treatment is performed to the top barrier layer so as to form a silicon-containing top barrier layer. A low-resistivity metal layer is formed in the gate trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.