Low resistance dual liner contacts for Fin Field-Effect Transistors (FinFETs)
US9768077B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2016 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Jun 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53266
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes first and second gate structures on a substrate respectively corresponding to an n-type and a p-type transistor, a first source/drain on the substrate corresponding to the n-type transistor, a second source/drain on the substrate corresponding to the p-type transistor, a first contact trench over the first source/drain and adjacent the first gate structure, a second contact trench over the second source/drain and adjacent the second gate structure, a first liner layer in the first trench positioned at a bottom part of the first trench, a second liner layer in the second trench and on the first liner layer in the first trench, a metallization layer in the first and second trenches on the second liner layer, and a first silicide contact between the first liner layer and the first source/drain and a second silicide contact between the second liner layer and the second source/drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.