Praneet Adusumilli
151Patents
8h-index
67Co-inventors
79Inventor score
Filing activity: Jan 20, 2010 → Jun 22, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9496225B1 | Recessed metal liner contact with copper fill | Electricity | 384 | Active |
| US9805989B1 | Sacrificial cap for forming semiconductor contact | Electricity | 22 | Active |
| US9741812B1 | Dual metal interconnect structure | Electricity | 22 | Active |
| US9768077B1 | Low resistance dual liner contacts for Fin Field-Effect Transistors (FinFETs) | Electricity | 16 | Active |
| US9437714B1 | Selective gate contact fill metallization | Electricity | 14 | Active |
| US10580966B1 | Faceted sidewall magnetic tunnel junction structure | Physics | 13 | Active |
| US10074727B2 | Low resistivity wrap-around contacts | Electricity | 13 | Active |
| US9935051B2 | Multi-level metallization interconnect structure | Electricity | 9 | Active |
| US9934977B1 | Salicide bottom contacts | Electricity | 7 | Active |
| US9978750B1 | Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices | Electricity | 7 | Active |
| US9722038B2 | Metal cap protection layer for gate and contact metallization | Electricity | 6 | Active |
| US9735165B1 | Vertically stacked FinFET fuse | Electricity | 6 | Active |
| US10049980B1 | Low resistance seed enhancement spacers for voidless interconnect structures | Electricity | 6 | Active |
| US9805973B2 | Dual silicide liner flow for enabling low contact resistance | Electricity | 5 | Active |
| US9613899B1 | Epitaxial semiconductor fuse for FinFET structure | Electricity | 4 | Active |
| US10388600B2 | Binary metallization structure for nanoscale dual damascene interconnects | Electricity | 4 | Active |
| US10090287B1 | Deep high capacity capacitor for bulk substrates | Electricity | 4 | Active |
| US10056391B2 | Vertically stacked FinFET fuse | Electricity | 4 | Active |
| US10269698B1 | Binary metallization structure for nanoscale dual damascene interconnects | Electricity | 4 | Active |
| US9859403B1 | Multiple step thin film deposition method for high conformality | Electricity | 4 | Active |
| US9831254B1 | Multiple breakdown point low resistance anti-fuse structure | Electricity | 4 | Active |
| US9570574B1 | Recessed metal liner contact with copper fill | Electricity | 4 | Active |
| US10340355B2 | Method of forming a dual metal interconnect structure | Electricity | 3 | Active |
| US9564310B1 | Metal-insulator-metal capacitor fabrication with unitary sputtering process | Electricity | 3 | Active |
| US10915811B1 | Intercalation cells for multi-task learning | Physics | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.