Vertical gate-all-around field effect transistors
US9768252B2 · kind B2 · utility
6Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2016 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Nov 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices and methods of forming the same are provided. A template layer is formed on a substrate, the template layer having a recess therein. A plurality of nanowires is formed in the recess. A gate stack is formed over the substrate, the gate stack surrounding the plurality of nanowires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.