Method and apparatus of forming an integrated circuit with a strained channel region
US9768277B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2015 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Jul 31, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various methods include providing a substrate, forming a projection extending upwardly from the substrate, the projection having a channel region therein, and forming a gate structure engaging the projection adjacent to the channel region, the gate structure having spaced first and second conductive layers and a strain-inducing conductive layer disposed between the first and second conductive layers. The method also includes forming epitaxial growths on portions of the projection at each side of the gate structure, the epitaxial growths imparting a first strain to the channel region, and imparting a second strain to the channel region, including performing at least one stress memorization technique on the gate structure such that the strain-inducing conductive layer imparts the second strain to the channel region, and removing the capping layer, wherein the imparting the second strain is carried out in a manner that imparts tensile strain to the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.