Short channel effect suppression
US9768301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2015 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Sep 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor substrate having a first region and a second region. The first region includes a first set of fin structures, the first set of fin structures comprising a first set of epitaxial anti-punch-through features of a first conductivity type. The first region further includes a first set of transistors formed over the first set of fin structures. The second region includes a second set of fin structures, the second set of fin structures comprising a second set of epitaxial anti-punch-through features of a second conductivity type opposite to the first conductivity type. The second region further includes a second set of transistors formed over the second set of fin structures. The first set of epitaxial anti-punch-through features and the second set of epitaxial anti-punch-through features are substantially co-planar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.