Manufacture method of dual gate oxide semiconductor TFT substrate and structure thereof
US9768323B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2017 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Mar 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1213
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual gate oxide semiconductor TFT substrate is made by utilizing a halftone mask to implement one photo process, which accomplishes patterning of an oxide semiconductor layer and forms an oxide conductor layer with ion doping process. Patterning of a bottom gate isolation layer and a top gate isolation layer are performed at the same time with one photo process. A first top gate, a first source, a first drain, a second top gate, a second source, and a second drain are formed at the same time with one photo process. Patterning of a flat layer, a passivation layer, and a top gate isolation layer are performed at the same time with one photo process. As such, the number of photo processes applied to manufacture the TFT substrate is reduced to five and the manufacturing process is shortened to thereby raise the production efficiency and lower the production cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.