High-throughput batch porous silicon manufacturing equipment design and processing methods
US9771662B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2015 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | Jul 6, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.