Semiconductor manufacturing method and tool
US9772561B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Jul 20, 2015 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | Jan 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An overlay measurement and correction method and device is provided. In an embodiment the measurement device takes measurements of a first semiconductor wafer and uses the measurements in a plurality of correction techniques to generate an overlay correction model. The plurality of correction techniques include a first order correction, a first intra-field high order parameter correction and a first inter-field high order parameter correction. The model is used to adjust the exposure parameters for the exposure of the next semiconductor wafer. The process is repeated on each semiconductor wafer for a run-to-run analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.