Multi-granular cache coherence
US9772950B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 25, 2012 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | Jan 31, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/301
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies are generally described for methods and systems effective to maintain coherence in a multi-core processor on a die. In an example, a method for processing a request for a particular block in a particular region may include analyzing, by a first processor, a first cache to determine whether there is a block indicator in the first cache associated with the particular block. The method may further include when the first processor determines that the block indicator is not present in the first cache, analyzing, by the first processor, the first cache to determine whether there is a region indicator associated with the particular region. The method may further include when the first processor determines that the region indicator is not present in the first cache, the method further includes sending, by the first processor, the request to the directory in the tile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.