Circuit design employing stamp patterns
US9773082B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2015 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | Dec 7, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems provide aspects of electronics layout design including copying of layout element(s) and graphically defining a one-to-one correspondence between two elements. An exemplary method may include defining a cloning constraint for a layout, rendering a user interface (UI) to display at least one of a schematic and form representation of the layout, and receiving a selection of at least one element in the layout. The method may create a movable drag set based on the selection, and responsive to a matching of at least one element of the drag set with another element in the layout, performing a one-to-one correspondence for the matched elements. The matching may be an overlap of at least one element in the drag set with an element in the layout having the same master.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.