Transistor performance modification with stressor structures

US9773793B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Scott R. Summerfelt · Dallas, US
• Rajni J. Aggarwal · Garland, US
• Shaoping Tang · Plano, US

Key dates

• Filing date: Oct 9, 2009
• Grant date: Sep 26, 2017
• Expiry date: May 6, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/792

Abstract

A transistor structure with stress enhancement geometry aligned above the channel region. Also, a transistor structure with stress enhancement geometries located above and aligned with opposite sides of the channel region. Furthermore, methods for fabricating integrated circuits containing transistors with stress enhancement geometries.