Relaxed semiconductor layers with reduced defects and methods of forming the same
US9773906B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2016 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | Jan 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a layer of silicon germanium include forming an epitaxial layer of Si1-xGex on a silicon substrate, wherein the epitaxial layer of Si1-xGex has a thickness that is less than a critical thickness, hc, at which threading dislocations form in Si1-xGex on silicon; etching the epitaxial layer of Si1-xGex to form Si1-xGex pillars that define a trench in the epitaxial layer of Si1-xGex, wherein the trench has a height and a width, wherein the trench has an aspect ratio of height to width of at least 1.5; and epitaxially growing a suspended layer of Si1-xGex from upper portions of the Si1-xGex pillars, wherein the suspended layer defines an air gap in the trench beneath the suspended layer of Si1-xGex.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.