Polishing stop layer(s) for processing arrays of semiconductor elements
US9773974B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2016 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | Apr 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
Abstract
Described embodiments can be used in semiconductor manufacturing and employ materials with high and low polish rates to help determine a precise polish end point that is consistent throughout a wafer and that can cease polishing prior to damaging semiconductor elements. The height of the low polish rate material between the semiconductor elements is used as the polishing endpoint. Because the low polish rate material slows down the polishing process, it is easy to determine an end point and avoid damage to the semiconductor elements. An additional or alternative etch end point can be a thin layer of material that provides a very clear spectroscopy signal when it has been exposed, allowing the etch process to cease.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.