Low power threshold integrated micro-plasma limiter
US9774067B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2015 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | May 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01T19/04
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A plasma power limiter fabricated using wafer-level fabrication techniques with other circuit elements. The power limiter includes a signal substrate having a first side and a second side, an input signal line formed on the first side, a signal transmission line formed on the second side and an output signal line formed on the first side. The power limiter also includes a ground substrate having a first side and a second side, and being bonded to the signal substrate to form a sealed cavity including an ionizable gas therebetween. The ground substrate includes a ground metal layer formed on the second side. A signal propagating on the input signal line at a power level greater than a threshold power level generates a voltage potential across the cavity that ionizes the gas and generates a plasma discharge, and limits power of the output signal coupled to the output signal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.