Method and system of merging memory cells into multi-bit registers in an integrated circuit layout
US9779197B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2015 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Aug 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system of merging one-bit cells in an integrated circuit layout, comprising a database to store the layout, a placer in communication with the database to update the layout, and a merger in communication with the placer. The merger is configured to: identify a set of one-bit cells in the integrated circuit layout; determine a set of merge cells, from among the identified set of one-bit cells, to be merged into a multi-bit register, the determination of the set of merge cells being based on each merge cell being located within a merge distance from each of the other merge cells in the set of merge cells, and each merge cell sharing a clock with the other merge cells in the set of merge cells; and generate instructions to the placer for merging the set of merge cells to form the multi-bit register in the integrated circuit layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.