Methods and apparatus for optimization of inspection speed by generation of stage speed profile and selection of care areas for automated wafer inspection
US9780004B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 2011 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Jun 14, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are apparatus and methods for the generation of a stage speed profile and/or the selection of care areas for automated wafer inspection. The stage speed profile generated corresponds to a fastest speed the inspection machine is able to inspect provided a set of care areas. The set of care areas selected correspond to specific regions on the wafer which are to be imaged in detail by the inspection machine. The apparatus and methods herein may also calculate speed of inspection and coverage (and possibly other characteristics of the inspection) for a quantity of cases, and select the best trade-off of coverage versus inspection time using a cost function. Other aspects, features, and embodiments of the invention are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.