Flash cell structure and method of fabricating the same
US9780101B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2016 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Nov 24, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/68
Abstract
The present invention provides a flash cell structure and a method of fabricating the same. The flash cell structure includes a semiconductor substrate, a stacked gate structure disposed on the semiconductor substrate, a first doped region disposed in the semiconductor substrate at a side of the stacked gate structure, a first dielectric layer, a second dielectric layer, and an erase gate. The stacked gate structure includes a floating gate insulated from the semiconductor substrate and a control gate disposed on the floating gate and insulated from the floating gate. The first dielectric layer is disposed on a sidewall of the floating gate. The second dielectric layer is disposed on the first doped region. A thickness of the first dielectric layer is less than a thickness of the second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.