Methods of forming integrated circuit devices
US9780107B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 15, 2015 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Dec 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming integrated circuit devices containing memory cells over a first region of a semiconductor substrate and gate structures over a second region of the semiconductor substrate recessed from the first region. The methods include forming a metal that is common to both the memory cells and the gate structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.