Composite wafer semiconductor devices using offset via arrangements and methods of fabricating the same
US9780136B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 22, 2016 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Sep 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/811
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A device includes a first integrated circuit substrate including a plurality of first metal layers interconnected by first vias and a second integrated circuit substrate on the first integrated circuit substrate and including second metal layers interconnected by second vias. An insulation layer is disposed between the first and second substrates and a connection region is disposed in the insulation layer and electrically connects a first one of the first metal layers to a first one of the second metal layers. The device further includes a bonding pad on the second substrate and a through via extending from the bonding pad and into the second to contact a second one of the second metal layers. The through via is positioned so as to not overlap at least one of the first vias, the second vias and the connection region. Methods of fabricating such device are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.